-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "04/15/2025 17:05:16"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	lab1 IS
    PORT (
	c3 : OUT std_logic;
	a : IN std_logic_vector(3 DOWNTO 0);
	b : IN std_logic_vector(3 DOWNTO 0);
	c0 : IN std_logic;
	codeout : OUT std_logic_vector(7 DOWNTO 0);
	sum : OUT std_logic_vector(3 DOWNTO 0)
	);
END lab1;

-- Design Ports Information
-- c3	=>  Location: PIN_AE8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[7]	=>  Location: PIN_M21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[6]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[5]	=>  Location: PIN_G14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[4]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[3]	=>  Location: PIN_G18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[2]	=>  Location: PIN_F18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[1]	=>  Location: PIN_G17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[0]	=>  Location: PIN_G16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- sum[3]	=>  Location: PIN_AE9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- sum[2]	=>  Location: PIN_AB9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- sum[1]	=>  Location: PIN_AE10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- sum[0]	=>  Location: PIN_AF10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[2]	=>  Location: PIN_AA8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[2]	=>  Location: PIN_AF12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[0]	=>  Location: PIN_AH12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[0]	=>  Location: PIN_AE4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- c0	=>  Location: PIN_AA10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[1]	=>  Location: PIN_AF14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[1]	=>  Location: PIN_AC5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[3]	=>  Location: PIN_AB8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[3]	=>  Location: PIN_AG12,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF lab1 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_c3 : std_logic;
SIGNAL ww_a : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_b : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_c0 : std_logic;
SIGNAL ww_codeout : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_sum : std_logic_vector(3 DOWNTO 0);
SIGNAL \c3~output_o\ : std_logic;
SIGNAL \codeout[7]~output_o\ : std_logic;
SIGNAL \codeout[6]~output_o\ : std_logic;
SIGNAL \codeout[5]~output_o\ : std_logic;
SIGNAL \codeout[4]~output_o\ : std_logic;
SIGNAL \codeout[3]~output_o\ : std_logic;
SIGNAL \codeout[2]~output_o\ : std_logic;
SIGNAL \codeout[1]~output_o\ : std_logic;
SIGNAL \codeout[0]~output_o\ : std_logic;
SIGNAL \sum[3]~output_o\ : std_logic;
SIGNAL \sum[2]~output_o\ : std_logic;
SIGNAL \sum[1]~output_o\ : std_logic;
SIGNAL \sum[0]~output_o\ : std_logic;
SIGNAL \a[3]~input_o\ : std_logic;
SIGNAL \a[2]~input_o\ : std_logic;
SIGNAL \b[1]~input_o\ : std_logic;
SIGNAL \b[0]~input_o\ : std_logic;
SIGNAL \c0~input_o\ : std_logic;
SIGNAL \a[0]~input_o\ : std_logic;
SIGNAL \inst|c1~1_combout\ : std_logic;
SIGNAL \a[1]~input_o\ : std_logic;
SIGNAL \inst|c1~0_combout\ : std_logic;
SIGNAL \inst1|c1~0_combout\ : std_logic;
SIGNAL \b[2]~input_o\ : std_logic;
SIGNAL \inst2|c1~1_combout\ : std_logic;
SIGNAL \b[3]~input_o\ : std_logic;
SIGNAL \inst2|c1~0_combout\ : std_logic;
SIGNAL \inst3|c1~0_combout\ : std_logic;
SIGNAL \inst1|ha2|s~combout\ : std_logic;
SIGNAL \inst3|ha2|s~combout\ : std_logic;
SIGNAL \inst2|ha2|s~0_combout\ : std_logic;
SIGNAL \inst|ha2|s~0_combout\ : std_logic;
SIGNAL \inst4|WideOr0~0_combout\ : std_logic;
SIGNAL \inst4|WideOr1~0_combout\ : std_logic;
SIGNAL \inst4|WideOr2~0_combout\ : std_logic;
SIGNAL \inst4|WideOr3~0_combout\ : std_logic;
SIGNAL \inst4|WideOr4~0_combout\ : std_logic;
SIGNAL \inst4|WideOr5~0_combout\ : std_logic;
SIGNAL \inst4|WideOr6~0_combout\ : std_logic;
SIGNAL \inst4|ALT_INV_WideOr6~0_combout\ : std_logic;
SIGNAL \inst4|ALT_INV_WideOr5~0_combout\ : std_logic;
SIGNAL \inst4|ALT_INV_WideOr4~0_combout\ : std_logic;
SIGNAL \inst4|ALT_INV_WideOr3~0_combout\ : std_logic;
SIGNAL \inst4|ALT_INV_WideOr2~0_combout\ : std_logic;
SIGNAL \inst4|ALT_INV_WideOr1~0_combout\ : std_logic;

BEGIN

c3 <= ww_c3;
ww_a <= a;
ww_b <= b;
ww_c0 <= c0;
codeout <= ww_codeout;
sum <= ww_sum;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\inst4|ALT_INV_WideOr6~0_combout\ <= NOT \inst4|WideOr6~0_combout\;
\inst4|ALT_INV_WideOr5~0_combout\ <= NOT \inst4|WideOr5~0_combout\;
\inst4|ALT_INV_WideOr4~0_combout\ <= NOT \inst4|WideOr4~0_combout\;
\inst4|ALT_INV_WideOr3~0_combout\ <= NOT \inst4|WideOr3~0_combout\;
\inst4|ALT_INV_WideOr2~0_combout\ <= NOT \inst4|WideOr2~0_combout\;
\inst4|ALT_INV_WideOr1~0_combout\ <= NOT \inst4|WideOr1~0_combout\;

-- Location: IOOBUF_X5_Y0_N23
\c3~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|c1~0_combout\,
	devoe => ww_devoe,
	o => \c3~output_o\);

-- Location: IOOBUF_X67_Y35_N2
\codeout[7]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \codeout[7]~output_o\);

-- Location: IOOBUF_X11_Y43_N16
\codeout[6]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|WideOr0~0_combout\,
	devoe => ww_devoe,
	o => \codeout[6]~output_o\);

-- Location: IOOBUF_X29_Y43_N23
\codeout[5]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|ALT_INV_WideOr1~0_combout\,
	devoe => ww_devoe,
	o => \codeout[5]~output_o\);

-- Location: IOOBUF_X41_Y43_N9
\codeout[4]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|ALT_INV_WideOr2~0_combout\,
	devoe => ww_devoe,
	o => \codeout[4]~output_o\);

-- Location: IOOBUF_X48_Y43_N16
\codeout[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|ALT_INV_WideOr3~0_combout\,
	devoe => ww_devoe,
	o => \codeout[3]~output_o\);

-- Location: IOOBUF_X54_Y43_N16
\codeout[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|ALT_INV_WideOr4~0_combout\,
	devoe => ww_devoe,
	o => \codeout[2]~output_o\);

-- Location: IOOBUF_X50_Y43_N23
\codeout[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|ALT_INV_WideOr5~0_combout\,
	devoe => ww_devoe,
	o => \codeout[1]~output_o\);

-- Location: IOOBUF_X43_Y43_N30
\codeout[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|ALT_INV_WideOr6~0_combout\,
	devoe => ww_devoe,
	o => \codeout[0]~output_o\);

-- Location: IOOBUF_X27_Y0_N23
\sum[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|ha2|s~combout\,
	devoe => ww_devoe,
	o => \sum[3]~output_o\);

-- Location: IOOBUF_X14_Y0_N16
\sum[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|ha2|s~0_combout\,
	devoe => ww_devoe,
	o => \sum[2]~output_o\);

-- Location: IOOBUF_X20_Y0_N16
\sum[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|ha2|s~combout\,
	devoe => ww_devoe,
	o => \sum[1]~output_o\);

-- Location: IOOBUF_X27_Y0_N9
\sum[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ha2|s~0_combout\,
	devoe => ww_devoe,
	o => \sum[0]~output_o\);

-- Location: IOIBUF_X0_Y3_N1
\a[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(3),
	o => \a[3]~input_o\);

-- Location: IOIBUF_X0_Y12_N22
\a[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(2),
	o => \a[2]~input_o\);

-- Location: IOIBUF_X0_Y2_N1
\b[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(1),
	o => \b[1]~input_o\);

-- Location: IOIBUF_X0_Y2_N15
\b[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(0),
	o => \b[0]~input_o\);

-- Location: IOIBUF_X18_Y0_N22
\c0~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_c0,
	o => \c0~input_o\);

-- Location: IOIBUF_X22_Y0_N1
\a[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(0),
	o => \a[0]~input_o\);

-- Location: LCCOMB_X20_Y4_N2
\inst|c1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst|c1~1_combout\ = (\c0~input_o\ & ((\b[0]~input_o\) # (\a[0]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[0]~input_o\,
	datab => \c0~input_o\,
	datad => \a[0]~input_o\,
	combout => \inst|c1~1_combout\);

-- Location: IOIBUF_X34_Y0_N1
\a[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(1),
	o => \a[1]~input_o\);

-- Location: LCCOMB_X20_Y4_N0
\inst|c1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst|c1~0_combout\ = (\b[0]~input_o\ & \a[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[0]~input_o\,
	datad => \a[0]~input_o\,
	combout => \inst|c1~0_combout\);

-- Location: LCCOMB_X20_Y4_N4
\inst1|c1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst1|c1~0_combout\ = (\b[1]~input_o\ & ((\inst|c1~1_combout\) # ((\a[1]~input_o\) # (\inst|c1~0_combout\)))) # (!\b[1]~input_o\ & (\a[1]~input_o\ & ((\inst|c1~1_combout\) # (\inst|c1~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[1]~input_o\,
	datab => \inst|c1~1_combout\,
	datac => \a[1]~input_o\,
	datad => \inst|c1~0_combout\,
	combout => \inst1|c1~0_combout\);

-- Location: IOIBUF_X25_Y0_N15
\b[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(2),
	o => \b[2]~input_o\);

-- Location: LCCOMB_X18_Y20_N2
\inst2|c1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|c1~1_combout\ = (\inst1|c1~0_combout\ & ((\a[2]~input_o\) # (\b[2]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \a[2]~input_o\,
	datac => \inst1|c1~0_combout\,
	datad => \b[2]~input_o\,
	combout => \inst2|c1~1_combout\);

-- Location: IOIBUF_X34_Y0_N22
\b[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(3),
	o => \b[3]~input_o\);

-- Location: LCCOMB_X18_Y20_N0
\inst2|c1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|c1~0_combout\ = (\a[2]~input_o\ & \b[2]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \a[2]~input_o\,
	datad => \b[2]~input_o\,
	combout => \inst2|c1~0_combout\);

-- Location: LCCOMB_X18_Y20_N28
\inst3|c1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|c1~0_combout\ = (\a[3]~input_o\ & ((\inst2|c1~1_combout\) # ((\b[3]~input_o\) # (\inst2|c1~0_combout\)))) # (!\a[3]~input_o\ & (\b[3]~input_o\ & ((\inst2|c1~1_combout\) # (\inst2|c1~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a[3]~input_o\,
	datab => \inst2|c1~1_combout\,
	datac => \b[3]~input_o\,
	datad => \inst2|c1~0_combout\,
	combout => \inst3|c1~0_combout\);

-- Location: LCCOMB_X20_Y4_N16
\inst1|ha2|s\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst1|ha2|s~combout\ = \b[1]~input_o\ $ (\a[1]~input_o\ $ (((\inst|c1~1_combout\) # (\inst|c1~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010110010110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[1]~input_o\,
	datab => \inst|c1~1_combout\,
	datac => \a[1]~input_o\,
	datad => \inst|c1~0_combout\,
	combout => \inst1|ha2|s~combout\);

-- Location: LCCOMB_X18_Y20_N24
\inst3|ha2|s\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|ha2|s~combout\ = \a[3]~input_o\ $ (\b[3]~input_o\ $ (((\inst2|c1~1_combout\) # (\inst2|c1~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010110010110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a[3]~input_o\,
	datab => \inst2|c1~1_combout\,
	datac => \b[3]~input_o\,
	datad => \inst2|c1~0_combout\,
	combout => \inst3|ha2|s~combout\);

-- Location: LCCOMB_X18_Y20_N22
\inst2|ha2|s~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|ha2|s~0_combout\ = \a[2]~input_o\ $ (\inst1|c1~0_combout\ $ (\b[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \a[2]~input_o\,
	datac => \inst1|c1~0_combout\,
	datad => \b[2]~input_o\,
	combout => \inst2|ha2|s~0_combout\);

-- Location: LCCOMB_X20_Y4_N6
\inst|ha2|s~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst|ha2|s~0_combout\ = \b[0]~input_o\ $ (\c0~input_o\ $ (\a[0]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001100101100110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[0]~input_o\,
	datab => \c0~input_o\,
	datad => \a[0]~input_o\,
	combout => \inst|ha2|s~0_combout\);

-- Location: LCCOMB_X18_Y20_N10
\inst4|WideOr0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr0~0_combout\ = (\inst|ha2|s~0_combout\ & ((\inst3|ha2|s~combout\) # (\inst1|ha2|s~combout\ $ (\inst2|ha2|s~0_combout\)))) # (!\inst|ha2|s~0_combout\ & ((\inst1|ha2|s~combout\) # (\inst3|ha2|s~combout\ $ (\inst2|ha2|s~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111010111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr0~0_combout\);

-- Location: LCCOMB_X18_Y20_N12
\inst4|WideOr1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr1~0_combout\ = (\inst1|ha2|s~combout\ & (!\inst3|ha2|s~combout\ & ((\inst|ha2|s~0_combout\) # (!\inst2|ha2|s~0_combout\)))) # (!\inst1|ha2|s~combout\ & (\inst|ha2|s~0_combout\ & (\inst3|ha2|s~combout\ $ (!\inst2|ha2|s~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110001100000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr1~0_combout\);

-- Location: LCCOMB_X18_Y20_N6
\inst4|WideOr2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr2~0_combout\ = (\inst1|ha2|s~combout\ & (!\inst3|ha2|s~combout\ & ((\inst|ha2|s~0_combout\)))) # (!\inst1|ha2|s~combout\ & ((\inst2|ha2|s~0_combout\ & (!\inst3|ha2|s~combout\)) # (!\inst2|ha2|s~0_combout\ & ((\inst|ha2|s~0_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011011100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr2~0_combout\);

-- Location: LCCOMB_X18_Y20_N16
\inst4|WideOr3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr3~0_combout\ = (\inst1|ha2|s~combout\ & ((\inst2|ha2|s~0_combout\ & ((\inst|ha2|s~0_combout\))) # (!\inst2|ha2|s~0_combout\ & (\inst3|ha2|s~combout\ & !\inst|ha2|s~0_combout\)))) # (!\inst1|ha2|s~combout\ & (!\inst3|ha2|s~combout\ & 
-- (\inst2|ha2|s~0_combout\ $ (\inst|ha2|s~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000100011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr3~0_combout\);

-- Location: LCCOMB_X18_Y20_N26
\inst4|WideOr4~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr4~0_combout\ = (\inst3|ha2|s~combout\ & (\inst2|ha2|s~0_combout\ & ((\inst1|ha2|s~combout\) # (!\inst|ha2|s~0_combout\)))) # (!\inst3|ha2|s~combout\ & (\inst1|ha2|s~combout\ & (!\inst2|ha2|s~0_combout\ & !\inst|ha2|s~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000011000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr4~0_combout\);

-- Location: LCCOMB_X18_Y20_N4
\inst4|WideOr5~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr5~0_combout\ = (\inst1|ha2|s~combout\ & ((\inst|ha2|s~0_combout\ & (\inst3|ha2|s~combout\)) # (!\inst|ha2|s~0_combout\ & ((\inst2|ha2|s~0_combout\))))) # (!\inst1|ha2|s~combout\ & (\inst2|ha2|s~0_combout\ & (\inst3|ha2|s~combout\ $ 
-- (\inst|ha2|s~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001100011100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr5~0_combout\);

-- Location: LCCOMB_X18_Y20_N14
\inst4|WideOr6~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|WideOr6~0_combout\ = (\inst3|ha2|s~combout\ & (\inst|ha2|s~0_combout\ & (\inst1|ha2|s~combout\ $ (\inst2|ha2|s~0_combout\)))) # (!\inst3|ha2|s~combout\ & (!\inst1|ha2|s~combout\ & (\inst2|ha2|s~0_combout\ $ (\inst|ha2|s~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100100100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst1|ha2|s~combout\,
	datab => \inst3|ha2|s~combout\,
	datac => \inst2|ha2|s~0_combout\,
	datad => \inst|ha2|s~0_combout\,
	combout => \inst4|WideOr6~0_combout\);

ww_c3 <= \c3~output_o\;

ww_codeout(7) <= \codeout[7]~output_o\;

ww_codeout(6) <= \codeout[6]~output_o\;

ww_codeout(5) <= \codeout[5]~output_o\;

ww_codeout(4) <= \codeout[4]~output_o\;

ww_codeout(3) <= \codeout[3]~output_o\;

ww_codeout(2) <= \codeout[2]~output_o\;

ww_codeout(1) <= \codeout[1]~output_o\;

ww_codeout(0) <= \codeout[0]~output_o\;

ww_sum(3) <= \sum[3]~output_o\;

ww_sum(2) <= \sum[2]~output_o\;

ww_sum(1) <= \sum[1]~output_o\;

ww_sum(0) <= \sum[0]~output_o\;
END structure;


